The present invention relates generally to programmable logic devices and, more particularly, to programmable gate arrays consisting of an array of logic blocks and input/output blocks with an interconnection structure, each of which are configurable by a configuration program stored in on chip memory.
The programmable gate array is a high performance, user programmable device containing three types of configurable elements that are customized to a user system design. The three elements are (1) an array of configurable logic blocks (CLBs), (2) with input/output blocks (IOBs) around a perimeter, all linked by (3) a flexible programmable interconnect network.
The system design desired by a user is implemented in the device by configuring programmable RAM cells. These RAM cells control the logic functionality performed by the CLBs, IOBs and the interconnect. The configuration is implemented using PGA design software tools.
It is generally accepted that the programmable gate array was first commercially introduced by Xilinx of San Jose, Calif. Xilinx originally introduced the XC2000 series of logic cell arrays and has more recently introduced a second generation XC3000 family of integrated circuit programmable gate arrays. A description of the 2000 series, as well as related programmable logic device art, can be found in THE PROGRAMMABLE GATE ARRAY DESIGN HANDBOOK, First Edition, published by Xilinx, pages 1-1 through 1-31. The architecture for the XC3000 family is provided in a technical data handbook published by Xilinx entitled XC3000 LOGIC CELL ARRAY FAMILY, pages 1-31. Each of these Xilinx publications is incorporated by reference in this application as providing a description of the prior art.
The prior art in programmable gate arrays is further exemplified by U.S. Pat. Nos. 4,642,487; 4,706,216; 4,713,557; and 4,758,985; each of which is assigned to Xilinx, Inc. These U.S. Patents are incorporated by reference as setting forth detailed descriptions of the programmable gate array architecture and implementations of the same.
As mentioned above, the programmable gate array consists of a configurable interconnect, a ring of configurable input/output blocks, and an array of configurable logic blocks. It is the combination of these three major features that provides flexibility and data processing power for programmable gate arrays. However, the programmable gate arrays of the prior art suffer certain limitations in each of the interconnect structure, the input/output block structures, and the configurable logic block structures.
The configurable interconnect structure must provide the ability to form networks on the programmable gate array which optimize utilization of the resources on the chip. The prior art interconnect systems have tended to force connection in the logical network to configurable blocks in a relatively small area. For instance, a prior system provides direct connections only between adjacent configurable logic blocks. The inputs and outputs on the configurable logic blocks are arranged in a left to right or otherwise asymmetrical layout that forces signal flow in a certain direction across the chip. This causes congestion on the interconnect structure for applications requiring a large number of inputs or outputs. Also, this forces the printed circuit board layout, which includes one of these asymmetrically designed logic cell arrays, to provide for inputs on one side of the logic cell array and outputs on the other.
In addition, the prior art interconnect structures are limited in the number of multi-source networks that can be implemented.
The input/output blocks in the prior art programmable gate arrays are relatively complex macro cells in order to provide flexibility needed for the wide variety of applications intended for the devices. However, these complex macro cells include resources that are unused in many configurations of the input/output blocks. Further, the blocks are relatively slow because of the complexity, requiring passage through a number of buffers, multiplexers and registers between the logic cells and the input/output pad. Furthermore, the input/output blocks cause congestion on the peripheral logic blocks in the device for applications involving a lot of input and output.
The configurable logic blocks themselves also suffer limitations which impact the flexibility of the device. The logic blocks of the prior art have operated upon a relatively small set of input variables. Thus, wide gating functions, such as decoding a 16 bit instruction or a wide multiplexing function, required cascading of many configurable blocks. Thus, a very simple function can utilize a large number of configurable logic blocks in the array. Further, when cascading blocks, due to the limitation of the number of direct interconnections between the logic blocks, many of the signals have to be transmitted across the programmable general connect. This causes delay because of the number of programmable interconnection points used. Further, for critical paths requiring fast operation, the cascading of blocks becomes impractical.
In the prior art configurable logic blocks, typically four input signals are used for the logic function. In order to obtain a five variable gating function, the configurable logic blocks used a sharing of inputs scheme. This sharing of inputs greatly limits the logic flexibility for these five variable functions in the prior art.
Prior art configurable logic blocks also suffered speed penalties because of the relatively complex structure required for the blocks to achieve user flexibility. For a block which is being used for a simple function, the logic would be propagated at a relatively slow rate because of the complex structures required.
It is desirable to provide a programmable gate array which provides for greater flexibility and logic power than provided by prior art devices.
The present invention provides an architecture for a configurable logic array with an interconnect structure which improves flexibility in creating networks to allow for greater utilization of the configurable logic blocks and input/output blocks on the device.
Accordingly, the present invention is an improved configurable logic array comprising a configuration memory storing program data specifying a user defined data processing function. In addition, a plurality of configurable logic blocks are arranged in an array consisting of C columns and R rows. Each configurable logic block is coupled to the configuration memory and has a plurality of inputs and outputs for generating output signals at the respective outputs in response to the input signals at the respective inputs and in response to program data in the configuration store. A plurality of configurable input/output blocks is included, each coupled to an input/output pad and to the configuration store, and having at least one input and at least one output. The configurable input/output blocks provide configurable interfaces between the respective pads and the respective inputs and outputs in response to the program data. A configurable interconnect is coupled to the configurable logic blocks, configurable input/output blocks and to the configuration store, for connecting the inputs and outputs of configurable logic blocks and configurable input/output blocks into logical networks in response to the program data in the configuration store.
According to one aspect of the invention, the configurable interconnect is symmetrically disposed relative to the inputs and outputs of the configurable logic blocks. Thus, inputs of the CLBs can be derived from four sides and outputs can be driven to four sides of the respective CLB into a symmetrical interconnect structure.
The interconnect includes a plurality of horizontal buses along the rows of CLBs and a plurality of vertical buses along the columns of CLBs. The intersections of the horizontal and vertical buses are configurable to route networks across the device.
Another aspect of the interconnect includes a plurality of switching matrices at the intersections of horizontal and vertical buses, each having a set of horizontal connections and a set of vertical connections, for interconnecting respective ones of the horizontal or vertical connections in response to program data in the configuration store. A plurality of horizontal conductive segments in the horizontal bus are connected between the horizontal connections of the switching matrices. A plurality of programmable interconnect points coupled to respective inputs and outputs of the configurable logic blocks and input/output blocks provide connectability to respective horizontal segments in response to program data. Likewise, a plurality of vertical conductive segments in the vertical bus are connected between the vertical connections of the adjacent switching matrices. Programmable interconnect points interconnect the respective inputs and outputs of configurable logic blocks and input/output blocks with respective vertical segments in response to the program data. The vertical and horizontal segments, according to one aspect of the invention, are characterized by extending from a switching matrix in a vertical or horizontal bus xe2x80x9cixe2x80x9d to switch matrix in bus xe2x80x9ci+2xe2x80x9d, so that each segment spans two columns or rows of logic blocks.
The buses in the interconnect are further characterized by a plurality of horizontal and vertical long conductive lines which extend across the entire chip. Each long line is connected to a plurality of programmable interconnect points for interconnecting the respective inputs or outputs of configurable logic cells with the respective long line in response to program data in the configuration memory. The long lines are characterized by having programmable interconnect points coupling an output of a configurable logic block which is supplied by a tristate buffer to the respective long lines.
In another aspect, the buses in the interconnect structure are characterized by uncommitted horizontal and vertical long lines. Each uncommitted long line is connected to a first plurality of programmable interconnect points for interconnecting the respective outputs of configurable logic blocks or input/output blocks with the respective long line in response to program data, and a second plurality of programmable interconnect points for interconnecting respective uncommitted long line with the horizontal or vertical segments that are coupled to the switching matrices.
The interconnect structure further includes a plurality of direct connections interconnecting an output of a configurable logic block or input/output block to an input of another configurable logic block or input/output block. The direct connections are characterized by including at least a first subset which are connected between adjacent input/output blocks or configurable logic blocks, and a second subset which are connected between the output of a configurable logic block or input/output block and a next adjacent configurable logic block or input/output block. In one aspect of the invention, each CLB is directly connected to 8 neighbor CLBs.
The plurality of configurable input/output blocks is characterized by groups of input/output blocks associated with each row or column of configurable logic blocks. Within each group, at least one complex input/output block is included and at least one simple input/output block. The complex input/output blocks provide the flexible functionality required for many applications, while the simple input/output block provides a fast access path into or out of the configurable array.
Further, all of the input/output logic blocks are characterized by tristatable output buffers to pads and to the internal interconnect which are controlled in response to the program data and/or a control signal generated in the configurable logic array.
Also, the outputs of the configurable logic blocks include a plurality of tristate buffers which receive respective ones of the output signals of the combinational logic and tristate control signals. The tristate output buffers supply a respective output signals or present a high impedance state as output from the logic block in response to the tristate control signal. The tristate control signal is generated in response to the program data in the configuration store and an input to the configurable logic block.
Another aspect of the invention is configurable repowering buffers with a bypass path coupled to the horizontal and vertical segments that go through switching matrices. Also, provision is made through the interconnect to supply control signals to all CLBs in the array from a single source.
The configurable logic blocks, according to the present invention, are characterized by a number of improvements over the prior art. In particular, the configurable logic blocks provide for a mixture of narrow gating and wide gating functions, which suffer a speed penalty only for the wide gating functions. Also, the configurable logic blocks are symmetrical, accepting inputs on four sides of each block and providing outputs on four sides. The output structures themselves provide the ability for tristating outputs connected to the configurable interconnect, and for directly driving signals to other configurable logic blocks.
The input structures on all four sides of the configurable logic blocks are independently configurable in response to the configuration program. Likewise, the four output macro cells in each configurable logic block are independently configurable.
As a feature that allows greater utilization of resources on the array, the registers in each of the output macro cells are accessible independently of the combinational logic in the configurable logic block. This allows these registers to be used in networks that are independent of the combinational logic.
According to one aspect, the configurable logic block can be characterized as having an input multiplexing tree which receives J input signals and selects a subset K signals, where K is less than or equal to J, in response to the program data. Combinational logic is coupled to the configuration memory and the input multiplexing tree, for generating a plurality of L logic signals in response to the K signals and the program data. Four independent output macro cells are included, each of which select output signals from the plurality of L logic signals.
Each of the output macro cells includes a tristatable output buffer for driving a selected output signal to the configurable interconnect. Also, each output macro cell includes a second output buffer, for driving a signal that is selected independently of the tristatable output buffer, for driving signals onto direct connections to other configurable logic blocks.
The input multiplexing tree is characterized by providing that any one of the K signals can be supplied from any of the four sides of the configurable iogic block.
The combinational logic is implemented with a first lookup table in the program data consisting of 64 bits which are grouped into eight 8 bit arrays. The 8 bit arrays are paired so that three independently supplied signals from the subset of K signals supplied by the input multiplexing tree are used to address each of the four pairs of 8 bit arrays. The two outputs of each pair are coupled to a cross-multiplexer which is configurable in response to the program data to directly pass through the two outputs supplied by the two 8 bit arrays in the pair, or to select one of the two outputs as a primary output in response to a fourth independently supplied signal from the subset K signals. The output of the cross-multiplexer is supplied through a third multiplexing level consisting of two multiplexers, each independently controllable by respective ones of the subset of K signals. The output of the third level of multiplexing is then supplied to a fourth level of multiplexing which is controlled by one of the subset of K signals, providing output which is a full lookup function of the 64 bit array in response to six inputs.
The combinational logic further includes a special 16 bit array in the program data which is coupled to a sixteen to one multiplexer. Control inputs to the sixteen to one multiplexer are the pass through outputs of the four cross-multiplexers referred to above. Each of these inputs is a function of four independent variables. The output of the sixteen to one multiplexer provides a special output, which provides a limited lookup function of the 16 independent variables. The special output is combined with the output of the fourth level multiplexer in a fifth level multiplexer, which is controlled in response to an input signal of the subset of K signals, or by the program data.
According to another aspect, the configurable logic block is characterized by a preload capability. During programming of the configurable logic array, each of the storage elements in the output macro cells of the configurable logic blocks is enabled to receive data as if it were a location in the configuration memory.
The configurable input/output architecture, according to the present invention, is characterized by a number of improvements over the prior art. In particular, the architecture provides for groups of input/output blocks associated with each row and column of configurable logic blocks in the array. Each of the groups is further characterized by having a plurality of complex input/output blocks, which provide flexible structures for implementing interfaces between the configurable logic array and outside devices, and at least one simple input/output block which provides a fast path from outside the device to the configurable logic array if required by a particular application.
Further, both the simple and complex input/output blocks are characterized by having at least one tristatable output buffer for driving signals onto the configurable interconnect structure, and a second buffer for driving direct connections to configurable logic blocks in the device.
The complex input/output blocks include an input storage element and an output storage element. A direct connection is provided from the input storage element of one complex input/output cell to a next adjacent complex input/output around the perimeter of the device. The output storage elements of the complex input/output cells are similarly connected. Thus, the storage elements in the complex input/output blocks can be linked into a configurable data path where they can be operated as a shift register or other similar circuit.
The storage elements in the complex input/output blocks are further configured to provide for synchronization functions, local readback functions, and buried register functions.
The input/output blocks, according to the present invention, are further characterized by control signal generation from the long lines in the programmable interconnect structure. This allows utilization of networks in the configurable logic array to control the operation and configuration of the configurable input/output blocks in a dynamic fashion. Also, the long lines are configured to propagate signals completely around the perimeter of the array, so that a common signal can be used to control all of the input/output blocks.
The configurable logic array provided, according to the present invention, greatly improves the flexibility and performance of programmable gate arrays over those available in the prior art. This is accomplished in part by an interconnect structure which supports networks with long reach across the device, multi-source networks, and symmetrical connections to the configurable logic blocks.
Further, a unique configurable logic block architecture supports efficient utilization of the resources in the array, wide gating functions, narrow gating functions without speed penalty and implementation of symmetrical networks in the array.
Finally, a unique input/output architecture supports efficient utilization of the resources in the input/output structures, allows for both fast signal propagation through the simple input/output blocks and high function signal propagation through the complex input/output blocks into the array, and has improved flexibility in the source of control signals for the input/output structure.
Further aspects and advantages of the present invention will be found upon review of the drawings, the detailed description and the claims which follow.